电子科技大学（深圳）高等研究院
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| 导师代码： |
21436
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| 导师姓名： |
龚江
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| 性 别： |
男 |
| 特 称： |
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| 职 称： |
教授
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| 学 位： |
哲学博士学位
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| 属 性： |
专职 |
| 电子邮件： |
gongjiang@uestc.edu.cn
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| 学术经历：
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2022.5 -- 2024.1
SiTime Corporation 资深模拟混合集成电路设计工程师
2024.1 -- 2024.12
苏黎世联邦理工大学 高级科学雇员/博士后
2024.12 -- 至今
电子科技大学（深圳）高等研究院 专任教师
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| 个人简介：
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龚江现为电子科技大学教授、博士生导师，长期致力于高性能时钟芯片的分析与设计研究，以及此方向在自动驾驶、****、消费电子等领域的产业化应用，设计并测试了10余款高性能时钟芯片。在集成电路领域重要会议和期刊上发表论文15篇(一作9篇)，其中8篇发表在集成电路顶级会议期刊IEEE ISSCC/JSSC上，Google scholar引用达300次。第一/共一作者发表的ISSCC/JSSC论文有5篇，具体包括：ISSCC 2020, ISSCC 2022, JSSC 2022, JSSC 2023，ISSCC 2025。研究成果被集成电路领域包括Behzad Razavi教授、Bram Nauta教授，Rui P. Martins教授和Robert Bogdan Staszewski教授等在内的多位专家引用。曾在美股上市公司SiTime带领团队全职从事基于MEMS时钟的量产工作，于2024年1月至11月在苏黎世联邦理工学院从事博士后工作。曾获得国家自然科学基金优秀青年科学基金项目(海外)，2021-2022 SSCS Predoctoral Achievement Award和国家优秀自费留学生奖学金，指导学生获得2023年国际微波会议最佳论文奖第二名。
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| 科研项目：
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| 研究成果：
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[1]. J. Gong, Y. Chen, F. Sebastiano, E. Charbon and M. Babaie, "19.3 A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications," 2020 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 308-310, doi: 10.1109/ISSCC19947.2020.9062913.
[2]. J. Gong, B. Patra, L. Enthoven, J. van Staveren, F. Sebastiano and M. Babaie, "A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoMA in 22nm FinFET," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731752.
[3]. J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A Cryo-CMOS PLL for Quantum Computing Applications," in IEEE Journal of Solid-State Circuits(JSSC), vol. 58, no. 5, pp. 1362-1375, May 2023, doi: 10.1109/JSSC.2022.3223629.
[4]. J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A Low-Jitter and Low-Spur Charge-Sampling PLL," in IEEE Journal of Solid-State Circuits(JSSC), vol. 57, no. 2, pp. 492-504, Feb. 2022, doi: 10.1109/JSSC.2021.3105335.
[5]. C. Livanelioglu*, L. He*, J. Gong*, S. Arjmandpour, G. Atzeni, T. Jang, “A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoMJ Including the XO Power and Noise,” 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025, (*共同一作)
[6]. J. Gong, Y. Chen, E. Charbon, F. Sebastiano and M. Babaie, "A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 12, pp. 4810-4822, Dec. 2022, doi: 10.1109/TCSI.2022.3199997.
[7]. J. Gong, F. Sebastiano, E. Charbon and M. Babaie, "A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter, -258.9 dB FOM and -65 dBc Reference Spur," 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Los Angeles, CA, USA, 2020, pp. 15-18, doi: 10.1109/RFIC49505.2020.9218380.
[8]. J. Gong et al., "A 1.33 mW, 1.6psrms-Integrated-Jitter, 1.8-2.7 GHz Ring-Oscillator-Based Fractional-N Injection-Locked DPLL for Internet-of-Things Applications," 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, PA, USA, 2018, pp. 44-47, doi: 10.1109/RFIC.2018.8429041.
[9]. J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications," 2021 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2021, pp. 1-2, doi: 10.1109/CICC51472.2021.9431541.
[10]. Y. Chen, J. Gong, R. B. Staszewski and M. Babaie, "A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <？54-dBc Spurs Under 50-mVpp Supply Ripple," in IEEE Journal of Solid-State Circuits(JSSC), vol. 57, no. 6, pp. 1749-1764, June 2022, doi: 10.1109/JSSC.2021.3123386.
[11]. Mehrpoo, Mohammadreza, Bishnu Patra, Jiang Gong, J. P. G. van Dijk, H. Homulle, G. Kiene, A. Vladimirescu, F. Sebastiano, E. Charbon, and M. Babaie. "Benefits and challenges of designing cryogenic CMOS RF circuits for quantum computers." In 2019 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5. IEEE, 2019.
[12]. Gao, Zhong, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen et al., "A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 380-382, doi: 10.1109/ISSCC42614.2022.9731561.
[13]. Gao, Zhong, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen et al., "A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit," in IEEE Journal of Solid-State Circuits(JSSC), vol. 58, no. 6, pp. 1552-1571, June 2023, doi: 10.1109/JSSC.2022.3209338.
[14]. Enthoven, Luc, Job Van Staveren, Jiang Gong, Masoud Babaie, and Fabio Sebastiano. "A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing." In 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 228-229. IEEE, 2022.
[15]. De Jong, Lennart, Joachim I. Bas, Jiang Gong, Fabio Sebastiano, and Masoud Babaie. "A 10-Gb/s 275-fsec jitter cryo-CMOS charge-sampling CDR for quantum computing application." IEEE Microwave and Wireless Technology Letters 33, no. 6 (2023): 875-878.
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| 专业研究方向：
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| 专业名称 |
研究领域/方向 |
招生类别 |
| 085400电子信息 |
01“电子科学与技术”研究方向组，05“电子科学与技术”研究方向组（非全） |
博士专业学位 |
| 085400电子信息 |
06微电子器件与集成电路（非全） |
硕士专业学位 |
| 085403集成电路工程 |
01微电子器件与集成电路 |
硕士专业学位 |
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